1. Field of the Invention
The present invention relates to a register file and operating system thereof in a microprocessor, and in particular, to a register file and operating system thereof in a microprocessor for performing a data transfer between repeater cells within a register file.
2. Background of the Related Art
As shown in FIG. 1, the operating system for a related art register file consists of a register file block 20, execution block 30 and control block 10.
The process for storing data in the related art register file block 20 will now be explained. According to control signals C-A, C-B and C-C from the control block 10, data are transferred from the execution block 30 to the register file block 20 by a third bus C-BUS. Data stored in the register file block 20 are emitted by first and second buses A-BUS, B-BUS. The execution block 30 carries out a particular function, e.g. an arithmetic operation with data from the register file block 20 carried on A-BUS and B-BUS after receiving a control signal C-exe from the control block 10. Then, the execution block 30 emits the result into the register file block 20 using the C-BUS. The control block 10 receives a clock signal CLOCK of a synchronous signal and data transfer order from an external device (not shown) and generates the first, second and third control signals C-A, C-B, C-C for controlling operation of the register file block 20 and the control signal C-exe for controlling operation of the execution block 30. Thus, the related art register file block 20 acts only as a memory device.
As shown in FIG. 2, a register cell making up a register file block 20 includes a first MOS transistor NM1 operating ON or OFF based on signals entered through its drain and gate. The drain is coupled to the C-BUS carrying data from the execution block 30 and the gate receives the third control signal C-C. Second and third MOS transistors NM2, NM3 also operate ON or OFF based on signals entered through their drains and gates. At this time, their drains are coupled to the output of a repeater cell 21 and the gates receive the control signals C-A and C-B from the control block 10, respectively.
The repeater cell 21 includes an inverter INV and two MOS transistors N1, P1, which operate to keep the input voltage state of the inverter INV by reverting the output signal from the inverter INV to maintain an output voltage state of the repeater cell 21. Further, the repeater cell may be composed of a positive or negative logic circuit for selecting its output signal.
A plurality of register cells forms a register file block such as the register block 20. As shown in FIG. 3, data from a source register cell enter the execution block 30 on the data path and the execution block 30 emits data into a destination register cell using the output bus C-BUS.
In a microprocessor with the related art register files, a data transfer between register cells requires an execution unit. Accordingly, the control block 10 receives the clock signal and the data transfer order to generate the appropriate control signals C-A, C-B, C-C. Thus, the overall efficiency of the microprocessor is reduced.
Each waveform of the control signals, input and output signals is illustrated in FIG. 4. Reference numbers 1 and 2 show a sequence of available signals during each signal output. First, when the third control signal C-C is high level when the third bus C-BUS is carrying a signal, the first MOS transistor NM1 operates, and the signal carried on the third bus C-BUS enters the repeater cell 21. Thus, the register file with a plurality of repeater cells stores data according to the signal carried on the C-BUS. At this time, when the first control signal C-1 or the second control signal C-B is high level, the data stored in the repeater cell 21 are respectively emitted by the A-BUS or the B-BUS.
In the related art register file, most registers can be designated a source or destination register. However, because some registers for logical multiply or any other particular purpose are exclusive, an additional transfer cycle between registers is needed for a data transfer from specific predetermined registers to another register. That is, an additional clock cycle and data transfer order are required.
As a result, the overall efficiency of a microprocessor is decreased. In other words, when the result from a logic operation within one register file is transferred to another register, the transfer time consumption reduces the efficiency of the microprocessor.